1. Field of the Invention
The present invention relates, in general, to a method for forming an interlayer insulating film of a semiconductor device and, more particularly, to the use of a high density plasma oxide film as a polishing retarder upon chemical mechanical polishing for the planarization of the interlayer insulating film.
2. Description of the Prior Art
The high step of semiconductor device, which is primarily created by the result of highly integrated semiconductor elements, probably causes so-called notching, a pattern defective problem resulting from the diffused reflection in the lithography process. It makes it difficult to progress to the subsequent process.
In order to solve this problem, planarizing techniques of burying the high step coverage with an insulating material have been suggested. These planarizing techniques are now considered to be a very important process in the high integration of a semiconductor device because they facilitate the subsequent processes.
Typically, in order to planarize a semiconductor device with high step coverage, a borophospho silicate glass (hereinafter referred to as "BPSG") film doped with high density boron (B) and phosphorous (P) is used, followed by treating it at high temperature.
However, this planarization process employing BPSG film still causes the notching problem in fabricating semiconductor devices with high integration degree, such as 256M DRAM or more, in which the step coverage between the cell area and the periphery area is maintained at a height of 0.8-1.0 .mu.m.
In addition, as metal wires are required to be narrower in semiconductor devices, a stepper employing shorter wave, such as deep UV, as a light source, is used for the photolithography thereof. However, the focus depth of such stepper becomes as small as about 0.4 .mu.m, which makes it impossible to form a photoresist pattern for metal wires. Although the photoresist pattern is formed, when it is used as a mask in a metal wiring process, either the resultant metal wires are likely to be intermitted or a bridge problem occurs. Here, the focus depth is defined as follows in order to forming a pattern on a wafer through an optical lens by use of an exposure mask. When a focus is brought into the wafer, virtual images appear on the upper and lower loci of the wafer based on the center of the lens. That is, the focus depth is twice of the length between the lens and the image nearest the lens.
A different method has been developed to overcome the above-mentioned difficulties in highly integrating semiconductor elements. A chemical mechanical polishing (hereinafter referred to as "CMP") technique using chemical slurry is currently used to polish and planarize the high step coverage.
A description of a conventional CMP technique with reference to FIGS. 1 and 2 will be given, in order to better understand the background of the invention.
First, as shown in FIG. 1, a semiconductor substrate 1 is prepared on which an infrastructure 3 is fabricated. It is obtained by forming a field oxidation film to separate semiconductor elements, forming a gate electrode, providing a source/drain electrode and forming a bit line and a capacitor. These are omitted in FIGS. 1 and 2 for convenience.
Then, a BPSG film 5 having about 1000 Angstrom thick, which is thicker than the step coverage between a cell area 100 and a periphery area 200, is deposited on the infrastructure 3, followed by the heat treatment of the BPSG film 5 at 800.degree. C. or higher.
Next, as shown in FIG. 2, a CMP process is executed to etch the BPSG film 5 for the planarization of the upper structure. At this time, the etching is effected on the periphery area 200 as well as the cell area 100. Therefore, although the step coverage denoted by "B" in FIG. 2 is smaller than the step denoted by "A" in FIG. 1, it still exists after the CMP process.
As described above, the CMP process allows the step coverage to be reduced by thickly depositing the BPSG film and mechanically polishing it with chemical reagent. However, owing to the CMP process's dishing effect that the cell area is polished along with the periphery area, it is difficult to obtain whole planarization and thus, the subsequent steps can not be processed smoothly. As a result, many problems arise, including difficulty in the high integration of a semiconductor device and degradation in the properties and the reliability of the semiconductor device thus obtained.
Since only a certain thickness of the BPSG film is polished, the conventional CMP additionally requires an end point detector, such as a detector for sensing the current change with motor speed or a detector of optical type. The point detects a factor in increasing the process cost of a semiconductor device. Moreover, the protocol to operate the detector adds complexity to the overall manufacture processing of a semiconductor device, resulting in a decrease in productivity.